The iPhone 5’s A6 system on a chip (SoC) contains 1 GB of RAM and utilizes a memory bandwidth that has a maximum speed of 8,528 MB/s, which is roughly 33 percent faster than the maximum memory bandwidth of the iPhone 4S, AnandTech revealed late Saturday.
According to AnandTech’s analysis, the A6 memory controller is a Samsung K3PE7E700F-XGC2, which is identified on the right side of the A6 chip cover. The “K3P” indicates dual-channel LPDDR2 (which stands for Low Power DDR2 memory) with 32-bit channels. The “E7E7” designation shows that each DRAM die contains 512 MB, for a total of 1 GB. The “C2” at the end of the package designation identifies the RAM cycle time and data rate, which is 1066 MHz.
With this information, AnandTech calculates that the iPhone 5’s maximum memory bandwidth is 8528 MB/s. Maximum memory bandwidth is theoretical, and actual bandwidth will usually be below the maximum rate. The higher threshold for the iPhone 5, however, does allow the phone’s processor to read and store data about 33 percent faster than its predecessor.
The iPhone 5’s bandwidth falls far short of that found in the third-generation iPad, but the lower resolution and graphical performance of the iPhone 5 means that significantly higher bandwidth rates are not yet a necessity on the smaller device.
Increased memory performance, 1 GB of RAM (up from 512 MB in the iPhone 4S), and a custom-designed processor architecture allow Apple to reach its advertised “2X” performance increase over the A5 SoC found in the iPhone 4S. We will soon see how well developers can take advantage of this increased performance.
The iPhone 5 launches Friday, September 21 at 8:00 a.m. local time. The initial batch of pre-orders has sold out, with mobile carriers and Apple now advertising “2-3 week” delivery estimates.